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gs8662dt07/10/19/37bd-450/400/350/333/300 72mb sigmaquad-ii+ tm burst of 4 sram 450 mhz?300 mhz 1.8 v v dd 1.8 v and 1.5 v i/o 165-bump bga commercial temp industrial temp rev: 1.00b 8/2017 1/28 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. features ? 2.0 clock latency ? simultaneous read and write sigmaquad? interface ? jedec-standard pinout and package ? dual double data rate interface ? byte write controls sampled at data-in time ? burst of 4 read and write ? dual-range on-die terminat ion (odt) on data (d), byte write ( bw ), and clock (k, k ) inputs ? 1.8 v +100/C100 mv core power supply ? 1.5 v or 1.8 v hstl interface ? pipelined read operation ? fully coherent read and write pipelines ? zq pin for programmable output drive strength ? data valid pin (qvld) supp ort ? ieee 1149.1 jtag-compliant boundary scan ? 165-bump, 13 mm x 15 mm, 1 mm bump pitch bga package ? rohs-compliant 165-bump bga pa ckage available sigmaquad? family overview the gs8662dt07/10/19/37bd are built in compliance with the sigmaquad-ii+ sram pinou t standard for separate i/o synchronous srams. they ar e 75,497,472-bit (72mb) srams. the gs8662dt07/10/19/37bd sigmaquad srams are just one element in a family of low power, low voltage hstl i/o srams designed to ope rate at the speeds needed to implement economical high performance networking systems. clocking and addr essing schemes the gs8662dt07/10/19/37bd sigmaquad-ii+ srams are synchronous devices. they empl oy two input register clock inputs, k and k . k and k are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. each internal read and write ope rat ion in a sigmaquad-ii+ b4 ram is four times wider than the device i/o bus. an input data bus de-multiplexer is used to accumulate incoming data before it is simultaneously wr itten to the memory array. an output data multiplexer is used to capture the data produced from a single memory array r ead and then route it to the appropriate output drivers as n eeded. therefore the address field of a sigmaquad-ii+ b4 ra m is always two address pins less than the advertised index depth (e.g., the 8m x 8 has a 2m addressable index). parameter synopsis -450 -400 -350 -333 -300 tkhkh 2.22 ns 2.5 ns 2.86 ns 3.0 ns 3.3 ns tkhqv 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.45 ns
8m x 8 sigmaquad-ii sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq sa sa w nw1 k nc/sa (144mb) r sa sa cq b nc nc nc sa nc/sa (288mb) k nw0 sa nc nc q3 c nc nc nc v ss sa nc sa v ss nc nc d3 d nc d4 nc v ss v ss v ss v ss v ss nc nc nc e nc nc q4 v ddq v ss v ss v ss v ddq nc d2 q2 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc d5 q5 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc q1 d1 k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc q6 d6 v ddq v ss v ss v ss v ddq nc nc q0 m nc nc nc v ss v ss v ss v ss v ss nc nc d0 n nc d7 nc v ss sa sa sa v ss nc nc nc p nc nc q7 sa sa qvld sa sa nc nc nc r tdo tck sa sa sa odt sa sa sa tms tdi 11 x 15 bump bga?13 x 15 mm body?1 mm bump pitch notes: 1. nw0 controls writes to d0:d3. nw1 controls writes to d4:d7. 2. pins a7 and b5 are the expansion addresses. gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 2/28 ? 2011, gsi technology
8m x 9 sigmaquad-ii sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq sa sa w nc k nc/sa (144mb) r sa sa cq b nc nc nc sa nc/sa (288mb) k bw0 sa nc nc q4 c nc nc nc v ss sa nc sa v ss nc nc d4 d nc d5 nc v ss v ss v ss v ss v ss nc nc nc e nc nc q5 v ddq v ss v ss v ss v ddq nc d3 q3 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc d6 q6 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc q2 d2 k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc q7 d7 v ddq v ss v ss v ss v ddq nc nc q1 m nc nc nc v ss v ss v ss v ss v ss nc nc d1 n nc d8 nc v ss sa sa sa v ss nc nc nc p nc nc q8 sa sa qvld sa sa nc d0 q0 r tdo tck sa sa sa odt sa sa sa tms tdi 11 x 15 bump bga?13 x 15 mm bo dy?1 mm bump pitch notes: 1. bw0 controls writes to d0:d8. 2. pins a7 and b5 are the expansion addresses. gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 3/28 ? 2011, gsi technology
4m x 18 sigmaquad-ii+ sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq nc/sa (144mb) sa w bw1 k nc/sa (288mb ) r sa sa cq b nc q9 d9 sa nc k bw0 sa nc nc q8 c nc nc d10 v ss sa nc sa v ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v ss v dd v ddq nc nc q5 g nc d13 q13 v ddq v dd v ss v dd v ddq nc nc d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d14 v ddq v dd v ss v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v ss v dd v ddq nc d3 q3 l nc q15 d15 v ddq v ss v ss v ss v ddq nc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss sa sa sa v ss nc nc d1 p nc nc q17 sa sa qvld sa sa nc d0 q0 r tdo tck sa sa sa odt sa sa sa tms tdi 11 x 15 bump bga?13 x 15 mm bo dy?1 mm bump pitch notes: 1. bw0 controls writes to d0:d8. bw1 controls writes to d9:d17. 2. pins a2 and a7 are the expansion addresses. gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 4/28 ? 2011, gsi technology
2m x 36 sigmaquad-ii+ sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq nc/sa (288mb ) sa w bw2 k bw1 r sa nc/sa (144mb) cq b q27 q18 d18 sa bw3 k bw0 sa d17 q17 q8 c d27 q28 d19 v ss sa nc sa v ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v ddq v ss v ss v ss v ddq q15 d6 q6 f q30 q21 d21 v ddq v dd v ss v dd v ddq d14 q14 q5 g d30 d22 q22 v ddq v dd v ss v dd v ddq q13 d13 d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j d31 q31 d23 v ddq v dd v ss v dd v ddq d12 q4 d4 k q32 d32 q23 v ddq v dd v ss v dd v ddq q12 d3 q3 l q33 q24 d24 v ddq v ss v ss v ss v ddq d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss sa sa sa v ss q10 d9 d1 p q35 d35 q26 sa sa qvld sa sa q9 d0 q0 r tdo tck sa sa sa odt sa sa sa tms tdi 11 x 15 bump bga?13 x 15 mm bo dy?1 mm bump pitch notes: 3. bw0 controls writes to d0:d8; bw1 controls writes to d9:d17; bw2 controls writes to d18:d26; bw3 controls writes to d27:d35 4. pins a2 and a10 are the expansion addresses. gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 5/28 ? 2011, gsi technology
pin description table symbol description type comments sa synchronous address inputs input ? r synchronous read input active low w synchronous write input active low bw0 ? bw3 synchronous byte writes input active low nw0 ? nw1 synchronous nybble writes input active low (x8 only) k input clock input active high k input clock input active low tms test mode select input ? tdi test data input input ? tck test clock input input ? tdo test data output output ? v ref hstl input reference voltage input ? zq output impedance matching input input ? qn synchronous data outputs output ? dn synchronous data inputs input ? doff disable dll when low input active low cq output echo clock output ? cq output echo clock output ? v dd power supply supply 1.8 v nominal v ddq isolated output buffer supply supply 1.8 v or 1.5 v nominal v ss power supply: ground supply ? qvld q valid output output ? odt on-die termination input low = low impedance range high/float = high impedance range nc no connect ? ? gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 6/28 ? 2011, gsi technology notes: 1. nc = not connected to die or any other pin 2. when zq pin is directly connected to v ddq , output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. k and k cannot be set to v ref voltage.
gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 7/28 ? 2011, gsi technology background separate i/o srams, from a system architecture point of view, a re attractive in applications where alternating reads and write s are needed. therefore, the sigmaquad-ii+ sram interface and truth t able are optimized for alternating reads and writes. separate i /o srams are unpopular in applications where multiple reads or mul tiple writes are needed because burst read or write transfers f rom separate i/o srams can cut the rams bandwidth in half. sigmaquad-ii+ b4 sram ddr read the status of the address input, w , and r pins are sampled by th e rising edges of k. w and r high causes chip disable. a low on the read enable pin, r , begins a read cycle. r is always ignored if the previo us command loaded was a read co mmand. clocking in a high on the read enable pin, r , begins a read por t deselect cycle. sram ddr write the status of the address input, w , and r pins are sampled by the rising edges of k. w and r high causes chip disable. a low on the write enable pin, w , and a high on the read enable pin, r , begins a write cycle. w is always ignored if the previous command was a write command. data is clocked in by the next rising edge of k, the rising edge of k after that, the next rising edge of k, and finally by the next rising edge of k . special functions byte write and nybble write control byte write enable pins are sampl ed at the same time that data in is sampled. a high on the byte write enable pin associated wi th a particular byte (e.g., bw0 controls d0Cd8 inputs) will inh ibit the storage of that partic ular byte, leaving wh atever data may be stored at the current address at that byte location undisturbed. any or all of the byte write enable pins may be driven high o r low during the data in sample times in a write sequence. each write enable command and wr ite addres s loaded into the ram provides the base address for a 4-beat data transfer. the x18 version of the ram, for example, may write 72 bits in associati on with each address loaded. any 9-bit byte may be masked in an y write sequence. nybble write (4-bit) control is implemented on the 8-bit-wide v ersion of t he device. for the x8 version of the device, nybbl e write enable and nwx may be substituted in a ll the discussion above. example x18 ram write sequence using byte write enables data in sample time bw0 bw1 d0?d8 d9?d17 beat 1 0 1 data in don?t care beat 2 1 0 don?t care data in beat 3 0 0 data in data in beat 4 1 0 don?t care data in resulting write operation byte 1 d0?d8 byte 2 d9?d17 byte 1 d0?d8 byte 2 d9?d17 byte 1 d0?d8 byte 2 d9?d17 byte 1 d0?d8 byte 2 d9?d17 written unchanged unchanged written written written unchanged written beat 1 beat 2 beat 3 beat 4
gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 8/28 ? 2011, gsi technology flxdrive-ii output driver impedance control hstl i/o sigmaquad-ii+ srams are supplied with programmable imp edance output drivers. the z q pin must be connected to v ss via an external resistor, rq, to allow the sram to monitor and adjust its output driver impeda nce. the value of rq must be 5x the value of the desired ram output impedance. the allowable range of rq to guarantee impedance matching continuously is between 175 ? and 350 ? . periodic readjustment of the output driver impedance is neces sary as the impedance is affected by drifts in supply voltage and temperatu re. the srams output impedance circuitry compensates for drifts in supply voltage and temperature. a clock cycle count er periodically triggers an impedance evaluation, resets and counts again. each impedance evaluation may move the output d river impedance level one step at a time towards the optimum l evel. the outp ut driver is implemented with dis crete binary weighted impedance steps. input termination impedance control these sigmaquad-ii+ srams are su pplied with programmable input termination on data (d), byte write ( bw ), and clock (k, k ) input receivers. the input termination is always enabled, and t he impedance is programmed via th e same rq resistor (connected between the zq pin and v ss ) used to program output driver impedance, in conjuction with t he odt pin (6r). when the odt pin is tied low, input termination is "strong" (i.e., low impedance ), and is nominally equal to rq*0.3 thevenin-equivalent when rq is between 175 and 350. when the odt pin is tied high (or left f loatingthe pin has a small pull-up resistor), input terminatio n is "weak" (i.e., high impedance) , and is nominally equal to rq* 0.6 thevenin-equivalent when r q is between 175 and 250. periodic readjustment of the term ination impedance occurs to co mpensate for drifts in supply voltage and temperature, in the s ame manner as for driver i mpedance (see above). note: d, bw , k, k inputs should always be driven high or low; they should never be tri-stated (i.e., in a high-z state). if the inputs are tri-stated, the input termination will pull the signal to v ddq /2 (i.e., to the switch point of the diff-amp receiver), which could cause the receiver to enter a meta-st able state, resulting in the rec eiver consuming more power than it normally would. this could r esult in the devices operati ng currents being higher. separate i/o sigmaquad ii + b4 sram truth table previous operation a r w current operation d d d d q q q q k ? (t n-1 ) k ? (t n ) k ? (t n ) k ? (t n ) k ? (t n ) k ? (t n+1 ) k ? (t n+1? ) k ? (t n+2 ) k ? (t n+2? ) k ? (t n+2) k ? (t n+2? ) k ? (t n+3 ) k ? (t n+3? ) deselect x 1 1 deselect x x ? ? hi-z hi-z ? ? write x 1 x deselect d2 d3 ? ? hi-z hi-z ? ? read x x 1 deselect x x ? ? q2 q3 ? ? deselect v 1 0 write d0 d1 d2 d3 hi-z hi-z ? ? deselect v 0 x read x x ? ? q0 q1 q2 q3 read v x 0 write d0 d1 d2 d3 q2 q3 ? ? write v 0 x read d2 d3 ? ? q0 q1 q2 q3 notes: 1. ?1? = input ?high?; ?0? = input ?low?; ?v? = input ?valid?; ?x? = input ?don?t care? 2. ??? indicates that the input requirement or output state is determined by the next operation. 3. q0, q1, q2, and q3 indicate the first, second, third, and f ourth pieces of output data tr ansferred during read operations. 4. d0, d1, d2, and d3 indicate the first, second, third, and f ourth pieces of input data tr ansferred during write operations. 5. users should not clock in metastable addresses.
x36 byte write enable ( bwn ) truth table bw0 bw1 bw2 bw3 d0?d8 d9?d17 d18?d26 d27?d35 1 1 1 1 don?t care don?t care don?t care don?t care 0 1 1 1 data in don?t care don?t care don?t care 1 0 1 1 don?t care data in don?t care don?t care 0 0 1 1 data in data in don?t care don?t care 1 1 0 1 don?t care don?t care data in don?t care 0 1 0 1 data in don?t care data in don?t care 1 0 0 1 don?t care data in data in don?t care 0 0 0 1 data in data in data in don?t care 1 1 1 0 don?t care don?t care don?t care data in 0 1 1 0 data in don?t care don?t care data in 1 0 1 0 don?t care data in don?t care data in 0 0 1 0 data in data in don?t care data in 1 1 0 0 don?t care don?t care data in data in 0 1 0 0 data in don?t care data in data in 1 0 0 0 don?t care data in data in data in 0 0 0 0 data in data in data in data in x18 byte write enable ( bwn ) truth table bw0 bw1 d0?d8 d9?d17 1 1 don?t care don?t care 0 1 data in don?t care 1 0 don?t care data in 0 0 data in data in x9 byte write enable ( bwn ) truth table bw0 d0?d8 1 don?t care 0 data in 1 don?t care 0 data in gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 9/28 ? 2011, gsi technology
x8 nybble write enable ( nwn ) truth table nw0 nw1 d0?d3 d4?d7 1 1 don?t care don?t care 0 1 data in don?t care 1 0 don?t care data in 0 0 data in data in gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 10/28 ? 2011, gsi technology
absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 2.9 v v ddq voltage in v ddq pins ?0.5 to v dd v v ref voltage in v ref pins ?0.5 to v ddq v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( ? 2.9 v max.) v v in input voltage (address, control, data, clock) ?0.5 to v ddq +0.5 ( ? 2.9 v max.) v v tin input voltage (tck, tms, tdi) ?0.5 to v ddq +0.5 ( ? 2.9 v max.) v i in input current on any pin +/?100 ma dc i out output current on any i/o pin +/?100 ma dc t j maximum junction temperature 125 o c t stg storage temperature ?55 to 125 o c note: permanent damage to the device may occur if the absolute maximu m ratings are exceeded. operati on should be restricted to recomm ended operating conditions. exposure to conditi ons exceeding the recommended operating condi tions, for an extended period of time, ma y affect reliability of this component. gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 11/28 ? 2011, gsi technology recommended oper ating conditions power supplies parameter symbol min. typ. max. unit supply voltage v dd 1.7 1.8 1.9 v i/o supply voltage v ddq 1.4 ? v dd v reference voltage v ref v ddq /2 ? 0.05 ? v ddq /2 + 0.05 v note: the power supplies need to be powered up simult aneo usly or in the following sequence: v dd , v ddq , v ref , followed by signal inputs. the power down sequence must be the reverse. v ddq must not exceed v dd . for more information, read an1021 sigmaquad and sigmaddr power-up. operating temperature parameter symbol min. typ. max. unit junction temperature (commercial range versions) t j 0 25 85 ?c junction temperature (industrial range versions)* t j ?40 25 100 ?c note: * the part numbers of industrial temperature range versions end with the character ?i?. unless otherwise noted, all performanc e specifications quoted are evaluated for worst case in the temperature range marked on the device.
thermal impedance package test pcb substrate ??ja (c/w) airflow = 0 m/s ? ja (c/w) airflow = 1 m/s ? ja (c/w) airflow = 2 m/s ??jb (c/w) ? jc (c/w) 165 bga 4-layer 22.300 18.572 17.349 9.292 2.310 notes: 1. thermal impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number. 2. please refer to jedec standard jesd51-6. 3. the characteristics of the test fixture pcb influence reported the rmal characteristics of the device. be advised that a good thermal path to the pcb can result in cooling or heating of the ram depending on pcb temperature. gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 12/28 ? 2011, gsi technology hstl i/o dc input characteristics parameter symbol min max units notes input reference voltage v ref v ddq /2 ? 0.05 v ddq /2 + 0.05 v ? input high voltage v ih1 v ref + 0.1 v ddq + 0.3 v 1 input low voltage v il1 ?0.3 v ref ? 0.1 v 1 input high voltage v ih2 0.7 * v ddq v ddq + 0.3 v 2,3 input low voltage v il2 ?0.3 0.3 * v ddq v 2,3 notes: 1. parameters apply to k, k , sa, d, r , w , bw during normal operation and jtag boundary scan testing. 2. parameters apply to doff , odt during normal operation an d jtag boundary scan testing. 3. parameters apply to zq during jtag boundary scan testing only. hstl i/o ac input characteristics parameter symbol min max units notes input reference voltage v ref v ddq /2 ? 0.08 v ddq /2 + 0.08 v ? input high voltage v ih1 v ref + 0.2 v ddq + 0.5 v 1,2,3 input low voltage v il1 ?0.5 v ref ? 0.2 v 1,2,3 input high voltage v ih2 v ddq ? 0.2 v ddq + 0.5 v 4,5 input low voltage v il2 ?0.5 0.2 v 4,5 notes: 1. v ih(max) and v il(min) apply for pulse widths less than one-quarter of the cycle time. 2. input rise and fall times must be a minimum of 1 v/ns, and within 10% of each other. 3. parameters apply to k, k , sa, d, r , w , bw during normal operation and jtag boundary scan testing. 4. parameters apply to d off , odt during normal operation an d jtag boundary scan testing. 5. parameters apply to zq during jtag boundary scan testing only.
capacitance o c, f = 1 mh z , v dd = 1.8 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 4 5 pf output capacitance c out v out = 0 v 6 7 pf clock capacitance c clk v in = 0 v 5 6 pf note: this parameter is sample tested. ac test conditions parameter conditions input high level 1.25 input low level 0.25 v max. input slew rate 2 v/ns input reference level 0.75 output reference level v ddq /2 note: test conditions as specified with output loading as shown unl ess otherwise noted. gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 13/28 ? 2011, gsi technology dq vt = = 0.75 v 50? rq = 250 ?? (hstl i/o) v ref = 0.75 v ac test load diagram input and output leakage characteristics parameter symbol test conditions min. max input leakage current (except mode pins) i il v in = 0 to v dd ?2 ua 2 ua doff i il doff v in = 0 to v dd ?2 ua 100 ua odt i il odt v in = 0 to v dd ?100 ua 2 ua output leakage current i ol output disable, v out = 0 to v ddq ?2 ua 2 ua (t a = 25
gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 14/28 ? 2011, gsi technology programmable impedance hstl output driver dc electrical characteristics parameter symbol min. max. units notes output high voltage v oh1 v ddq /2 ? 0.12 v ddq /2 + 0.12 v 1, 3 output low voltage v ol1 v ddq /2 ? 0.12 v ddq /2 + 0.12 v 2, 3 output high voltage v oh2 v ddq ? 0.2 v ddq v 4, 5 output low voltage v ol2 vss 0.2 v 4, 6 notes: 1. i oh = (v ddq /2) / (rq/5) +/? 15% @ v oh = v ddq /2 (for: 175? ?? rq ? 350 ??? 2. i ol = (v ddq /2) / (rq/5) +/? 15% @ v ol = v ddq /2 (for: 175 ? ? rq ? 350?? . 3. parameter tested with rq = 250 ? and v ddq = 1.5 v 4. 0 ???? rq ? ?? 5. i oh = ?1.0 ma 6. i ol = 1.0 ma operating currents parameter symbol test conditions -450 -400 -350 -333 -300 notes 0 to 70c C 40 to 85c 0 to 70 c C 40 to 85c 0 to 70c C 40 to 85c 0 to 70c C 40 to 85c 0 to 70 c C 40 to 85c operating current (x36): dd r i dd v dd = max, i out = 0 ma cycle time ?? t khkh min 1055 ma 1065 ma 940 ma 950 ma 885 ma 895 ma 810 ma 820 ma 735 ma 745 ma 2, 3 operating current (x18): dd r i dd v dd = max, i out = 0 ma cycle time ?? t khkh min 820 ma 830 ma 735 ma 745 ma 695 ma 705 ma 630 ma 640 ma 580 ma 590 ma 2, 3 operating current (x9): dd r i dd v dd = max, i out = 0 ma cycle time ?? t khkh min 820 ma 830 ma 735 ma 745 ma 695 ma 705 ma 630 ma 640 ma 580 ma 590 ma 2, 3 operating current (x8): dd r i dd v dd = max, i out = 0 ma cycle time ?? t khkh min 820 ma 830 ma 735 ma 745 ma 695 ma 705 ma 630 ma 640 ma 580 ma 590 ma 2, 3 standby current (n op): ddr i sb1 device deselected, i out = 0 ma, f = max, all inputs ?? 0.2 v or ?? v dd ? 0.2 v 270 ma 280 ma 260 ma 270 ma 250 ma 260 ma 240 ma 250 ma 230 ma 240 ma 2, 4 notes: 1. power measured with output pins floating. 2. minimum cycle, i out = 0 ma 3. operating current is calculated with 5 0% read cycles and 50% write cycles. 4. standby current is only after all pending r ead and write burst operations are complete d.
ac electrical characteristics parameter symbol -450 -400 -350 -333 -300 units notes min max min max min max min max min max clock k, k clock cycle time t khkh 2.22 8.4 2.5 8.4 2.86 8.4 3.0 8.4 3.3 8.4 ns tk variable t kvar ? 0.2 ? 0.2 ? 0.2 ? 0.2 ? 0.2 ns 4 k, k clock high pulse width t khkl 0.4 ? 0.4 ? 0.4 ? 0.4 ? 0.4 ? cycle k, k clock low pulse width t klkh 0.4 ? 0.4 ? 0.4 ? 0.4 ? 0.4 ? cycle k to k high t kh k h 0.94 ? 1.06 ? 1.13 ? 1.28 ? 1.32 ? ns k to k high t k hkh 0.94 ? 1.06 ? 1.13 ? 1.28 ? 1.32 ? ns dll lock time t klock 2048 ? 2048 ? 2048 ? 2048 ? 2048 ? cycle 5 k static to dll reset t kreset 30 ? 30 ? 30 ? 30 ? 30 ? ns output times k, k clock high to data output valid t khqv ? 0.45 ? 0.45 ? 0.45 ? 0.45 ? 0.45 ns k, k clock high to data output hold t khqx ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ns k, k clock high to echo clock valid t khcqv ? 0.45 ? 0.45 ? 0.45 ? 0.45 ? 0.45 ns k, k clock high to echo clock hold t khcqx ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ns cq, cq high output valid t cqhqv ? 0.15 ? 0.2 ? 0.23 ? 0.25 ? 0.27 ns cq, cq high output hold t cqhqx ?0.15 ? ?0.2 ? ?0.23 ? ?0.25 ? ?0.27 ? ns cq, cq high to qvld t qvld ?0.15 0.15 ?0.2 0.2 ?0.23 0.23 ?0.25 0.25 ?0.27 0.27 ns cq phase distortion t cqh cq h t c q hcqh 0.85 ? 1.0 ? 1.08 ? 1.25 ? 1.29 ? ns k clock high to data output high-z t khqz ? 0.45 ? 0.45 ? 0.45 ? 0.45 ? 0.45 ns k clock high to data output low-z t khqx1 ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ns setup times address input setup time t avkh 0.275 ? 0.4 ? 0.4 ? 0.4 ? 0.4 ? ns 1 control input setup time ( r , w ) t ivkh 0.275 ? 0.4 ? 0.4 ? 0.4 ? 0.4 ? ns 2 control input setup time ( bwx ) t ivkh 0.22 ? 0.28 ? 0.28 ? 0.28 ? 0.28 ? ns 3 data input setup time t dvkh 0.22 ? 0.28 ? 0.28 ? 0.28 ? 0.28 ? ns hold times address input hold time t khax 0.275 ? 0.4 ? 0.4 ? 0.4 ? 0.4 ? ns 1 control input hold time ( r , w ) t khix 0.275 ? 0.4 ? 0.4 ? 0.4 ? 0.4 ? ns 2 control input hold time ( bwx ) t khix 0.22 ? 0.28 ? 0.28 ? 0.28 ? 0.28 ? ns 3 data input hold time t khdx 0.22 ? 0.28 ? 0.28 ? 0.28 ? 0.28 ? ns notes: 1. all address inputs must meet the specified setup and hold times for all latching clock edges. 2. control signals are r , w . 3. control signals are bw0 , bw1 and ( bw2 , bw3 for x36). 4. clock phase jitter is the variance from cloc k rising edge to the next expected clock rising edge. 5. v dd slew rate must be less than 0.1 v dc per 50 ns for dll lock retention. dll lock time begins once v dd and input clock are stable. gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 15/28 ? 2011, gsi technology
read nop cq-base d timing diagram read a0 write noop read a1 write noop noop noop noop a0 a1 q0 q0+1 q0+2 q0+3 q1 q1+1 q1+2 q1+3 tqvld tcqlqx tcqhqx tcqhqv tcqlqv tqvld tcqhqx tcqlqx tcqlqv tcqhqv tkhix tivkh tkhix tivkh tkhax tavkh k k addr r w qvld q cq cq gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 16/28 ? 2011, gsi technology
read-write cq-based timing diagram read a0 write a1 read a2 write a3 noop noop noop a0 a1 a2 a3 d1 d1+1 d1+2 d1+3 d3 d3+1 d3+2 d3+3 q0 q0+1 q0+2 q0+3 q2 q2+1 q2+2 q2+3 tqvld tcqhqx tcqhqv tcqlqx tcqlqv tqvld tcqlqx tcqlqv tcqhqx tcqhqv tkhdx tdvkh tkhdx tdvkh tkhix tivkh tkhix tivkh tkhix tivkh tkhix tivkh tkhax tavkh k k addr r w bw x d qvld q cq cq gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 17/28 ? 2011, gsi technology
write nop timing diagram write a read no-op write b read no-op no-op no-op no-op a0 a1 d0 d0+1 d0+2 d0+3 d1 d1+1 d1+2 d1+3 tkhdx tdvkh tkhix tivkh tkhix tivkh tkhix tivkh tkhix tivkh tkhax tavkh k k addr r w bwx d gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 18/28 ? 2011, gsi technology
gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 19/28 ? 2011, gsi technology jtag port operation overview the jtag port on this ram operate s in a manner th at is complian t with ieee standard 1149.1-1 990, a serial boundary scan interface standard (commonly refe rred to as jtag). the jtag por t input interface le vels scale with v dd . the jtag output drivers are powered by v dd . disabling the jtag port it is possible to use this device w ithout utilizing the jtag po rt. the port is reset at power-up and will remai n inactive unle ss clocked. tck, tdi, and tms are designed with internal pull-up circuits.to assure normal opera tion of the ram with the jtag port unused, tck, tdi, and tms ma y be left floating or tied to either v dd or v ss . tdo should be left unconnected. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all inputs are captured on the rising edge of tck and all outputs propagate from the fa lling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state m achine. an undriven tms input will produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed b etween tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controller state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap state machine. output changes in response to the fa lling edge of tck. this is the output side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap reset) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap cont roller is also reset automaticly at power-up. jtag port registers overview the various jtag regist ers, refered to as t es t access port or t ap registers, are selected (one a t a time) via the sequences of 1s and 0s applied to tms as tck is strobed. each of the tap regist ers is a serial shift register t hat captures serial input data on the rising edge of tck and pushes serial data out on the next fall ing edge of tck. when a register is selected, it is placed betw een the tdi and tdo pins. instruction register the instruction register holds the instructions that are execut ed by the tap controller when it is moved into the run, test/id le, or the various data register states . instructions are 3 bits long. the instruction register can be loaded when it i s placed between the tdi and tdo pins. the instruction register is automatically pre loaded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed b etween tdi and tdo. it allows serial test data to be passed t hrough the rams jtag port to anothe r device in the scan chain with as little delay as possible. boundary scan register the boundary scan register is a co llection of flip flops that c an be preset by the logic level found on the rams input or i/o pins. the flip flops are then daisy ch ained together so the levels fo und can be shifted serially out o f the jtag ports tdo pin. th e boundary scan register also incl udes a number of place holder flip flops (always set to a logi c 1). the relationship between the device pins and the bits in the boundary scan register is descr ibed in the scan ord er table following. the boundary scan
gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 20/28 ? 2011, gsi technology register, under the control of t he tap controller, is loaded wi th the contents of the rams i/o r ing when the controller is in capture-dr state and then is placed between the tdi and tdo pin s when the controller is moved to shift-dr state. sample-z, sample/preload and extest instruct ions can be used to activate the boundary scan register. instruction register id code register boundary scan register 012 0 31 30 29 12 0 bypass register tdi tdo tms tck test access port (tap) controller 108 1 0 control signals jtag tap block diagram identification (id) register the id register is a 32-bit register that is loaded with a devi ce and ven dor specific 32-bit code when the controller is put i n capture-dr state with the idcode command loaded in the instruct ion register. the code is load ed from a 32-bit on-chip rom. it describes various attributes o f the ram as indicated below. the register is then placed betw een the tdi and tdo pins when t he controller is moved into shift-dr state. bit 0 in the register is the lsb and the f irst to reach tdo when shifting begins. id register contents see bsdl model gsi technology jedec vendor id code presence register bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x x x x x x x x x x x x x 0 0 0 1 1 0 1 1 0 0 1 1
gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 21/28 ? 2011, gsi technology tap controller instruction set overview there are two classes of in structions defined in the standard 1 149.1-1990; the standard (public) instructions, and device spec ific (private) instructions. some publ ic instructions are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. t he tap on this device may be u sed to monitor all input and i/o pads, and can be used to load address, data or control signals into the ram or to preload the i/o buffers. when the tap controller is placed in c apture-ir state the two l east significant bits of the inst ruction register are loaded wi th 01. when the controller is moved to the shift-ir state the instruct ion register is placed between tdi and tdo. in this state the d esired instruction is serially loaded t hrough the tdi input (while the previous contents are shifted out at tdo). for all instruction s, the tap executes newly loaded instructions only when the controller is moved to update-ir state. th e tap instruction set for this device is listed in the following table. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 11 1 jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction regist er the bypass register is placed between tdi and tdo. this occurs when the tap co ntroller is moved to the shift-dr state. this allows the board level scan path to be shortened to facili - tate testing of other dev ices in the scan path. sample/preload sample/preload is a standard 1149.1 mandatory public instructio n . when the sample / preload instruction is
gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 22/28 ? 2011, gsi technology loaded in the instruction regist er, moving the tap controller i nto the capture-dr state loads t he data in the rams input and i/o buffers into the boundary scan register. boundary scan regi ster locations are not associated with an input or i/o pin, and are loaded with the default stat e identified in the boundary sc an chain table at the end of this section of the datasheet. bec ause the ram clock is independent from the tap clock (tck) it is pos sible for the tap to attempt to capture the i/o ring contents while the input buffers are in t ransition (i.e. in a metastable state). although allowing the tap to sample metastable inputs will not harm the device, r epeatable results can not be expected. ram input signals must be stabilized for long enough to meet the taps input data capture set-up pl us hold time (tts plus tth). t he rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the bound ary scan register. moving the c ontroller to shift-dr state then places the boundary scan register between the tdi and tdo pins. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instr uction register is loaded with all logic 0s. the extest command does not block or override the rams input pins; therefore, the rams internal state is still determined by its input pins. ? ? typically, the boundary scan r egister is loaded with the desire d pattern of data with the sample/preload command. then the extest command is used to output the boundary scan reg isters contents, in parallel, on the rams data output drivers on the falling edge of tck when the controller is in th e update-ir state. ? ? alternately, the boundary scan register may be loaded in parall el using the extest comman d. when the extest instruc - tion is selected, the sate of all the rams input and i/o pins, as well as the default values a t scan register locations not a sso - ciated with a pin, are transferred in parallel into the boundar y scan register on the rising ed ge of tck in the capture-dr state, the rams output pins drive out the value of the boundar y scan register location with w hich each output pin is associ - ated. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between t he tdi and tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is l oad ed in the instruction regist er, all ram outputs are forced to an inactive drive state (high - z) and the boundary scan register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. jtag tap instruction set summary instruction code description notes extest 000 places the boundary scan register between tdi and tdo. 1 idcode 001 preloads id register and places it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all ram output drivers to high-z. 1 gsi 011 gsi private instruction. 1 sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. 1 gsi 101 gsi private instruction. 1 gsi 110 gsi private instruction. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state.
gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 23/28 ? 2011, gsi technology jtag port recommended operating conditions and dc characteristics parameter symbol min. max. unit notes test port input low voltage v ilj C 0.3 0.3 * v dd v 1 test port input high voltage v ihj 0.7 * v dd v dd +0.3 v 1 tms, tck and tdi input leakage current i inhj C 300 1 ua 2 tms, tck and tdi input leakage current i inlj C 1 100 ua 3 tdo output leakage current i olj C 1 1 ua 4 test port output high voltage v ohj v dd ? 0.2 v 5, 6 test port output low voltage v olj 0.2 v 5, 7 test port output cmos high v ohjc v dd ? 0.1 v 5, 8 test port output cmos low v oljc 0.1 v 5, 9 notes: 1. input under/overshoot voltage must be C 1 v < v i < v ddn +1 v not to exceed v maximum, with a pulse width not to exceed 20% ttkc. 2. v ilj ? v in ?? v ddn 3. 0 v ?? v in ?? v iljn 4. output disable, v out = 0 to v ddn 5. the tdo output driver is served by the v dd supply. 6. i ohj = C 2 ma 7. i olj = + 2 ma 8. i ohjc = ?100 ua 9. i oljc = +100 ua notes: 1. include scope and jig capacitance. 2. test conditions as shown unless otherwise noted. jtag port ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v dd /2 output reference level v dd /2 tdo v dd /2 50? 30pf * jtag port ac test load * distributed test jig capacitance
gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 24/28 ? 2011, gsi technology jtag port timing diagram tth tts ttkq tth tts tth tts ttklttkl ttkhttkh ttkcttkc tck tdi tms tdo parallel sram input jtag port ac electri cal characteristics parameter symbol min max unit tck cycle time ttkc 50 ? ns tck low to tdo valid ttkq ? 20 ns tck high pulse width ttkh 20 ? ns tck low pulse width ttkl 20 ? ns tdi & tms set up time tts 10 ? ns tdi & tms hold time tth 10 ? ns
gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 25/28 ? 2011, gsi technology package dimensions?165-b ump fpbga (package d) a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 a1 corner top view a1 corner bottom view 1.0 1.0 10.0 1.0 1.0 14.0 130.05 150.05 a b 0.20(4x) ?0.10 ?0.25 c c a b m m ?0.40~0.60 (165x) c seating plane 0.15 c 0.36~0.46 1.40 max.
gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 26/28 ? 2011, gsi technology ordering information?gs i sigmaquad-ii+ sram org part number 1 type package speed (mhz) t j 2 8m x 8 gs8662dt07bd-450 sigmaquad-ii+ b4 sram 165-bump bga 450 c 8m x 8 gs8662dt07bd-400 sigmaquad-ii+ b4 sram 165-bump bga 400 c 8m x 8 gs8662dt07bd-350 sigmaquad-ii+ b4 sram 165-bump bga 350 c 8m x 8 gs8662dt07bd-333 sigmaquad-ii+ b4 sram 165-bump bga 333 c 8m x 8 gs8662dt07bd-300 sigmaquad-ii+ b4 sram 165-bump bga 300 c 8m x 8 gs8662dt07bd-450i sigmaquad-ii+ b4 sram 165-bump bga 450 i 8m x 8 gs8662dt07bd-400i sigmaquad-ii+ b4 sram 165-bump bga 400 i 8m x 8 gs8662dt07bd-350i sigmaquad-ii+ b4 sram 165-bump bga 350 i 8m x 8 gs8662dt07bd-333i sigmaquad-ii+ b4 sram 165-bump bga 333 i 8m x 8 gs8662dt07bd-300i sigmaquad-ii+ b4 sram 165-bump bga 300 i 8m x 8 gs8662dt07bgd-450 sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 450 c 8m x 8 gs8662dt07bgd-400 sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 400 c 8m x 8 gs8662dt07bgd-350 sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 350 c 8m x 8 gs8662dt07bgd-333 sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 333 c 8m x 8 gs8662dt07bgd-300 sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 300 c 8m x 8 gs8662dt07bgd-450i sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 450 i 8m x 8 gs8662dt07bgd-400i sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 400 i 8m x 8 gs8662dt07bgd-350i sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 350 i 8m x 8 gs8662dt07bgd-333i sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 333 i 8m x 8 gs8662dt07bgd-300i sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 300 i 8m x 9 gs8662dt10bd-450 sigmaquad-ii+ b4 sram 165-bump bga 450 c 8m x 9 gs8662dt10bd-400 sigmaquad-ii+ b4 sram 165-bump bga 400 c 8m x 9 gs8662dt10bd-350 sigmaquad-ii+ b4 sram 165-bump bga 350 c 8m x 9 gs8662dt10bd-333 sigmaquad-ii+ b4 sram 165-bump bga 333 c 8m x 9 gs8662dt10bd-300 sigmaquad-ii+ b4 sram 165-bump bga 300 c 8m x 9 gs8662dt10bd-400i sigmaquad-ii+ b4 sram 165-bump bga 450 i 8m x 9 gs8662dt10bd-450i sigmaquad-ii+ b4 sram 165-bump bga 400 i 8m x 9 gs8662dt10bd-350i sigmaquad-ii+ b4 sram 165-bump bga 350 i 8m x 9 gs8662dt10bd-333i sigmaquad-ii+ b4 sram 165-bump bga 333 i 8m x 9 gs8662dt10bd-300i sigmaquad-ii+ b4 sram 165-bump bga 300 i 8m x 9 gs8662dt10bgd-450 sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 450 c 8m x 9 gs8662dt10bgd-400 sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 400 c notes: 1. for tape and reel add the character ?t? to the end of the part number. example: gs8662dtxxd-300t. 2. c = commercial temperature range. i = industrial temperature range.
gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 27/28 ? 2011, gsi technology 8m x 9 gs8662dt10bgd-350 sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 350 c 8m x 9 gs8662dt10bgd-333 sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 333 c 8m x 9 gs8662dt10bgd-300 sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 300 c 8m x 9 gs8662dt10bgd-450i sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 450 i 8m x 9 gs8662dt10bgd-400i sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 400 i 8m x 9 gs8662dt10bgd-350i sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 350 i 8m x 9 gs8662dt10bgd-333i sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 333 i 8m x 9 gs8662dt10bgd-300i sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 300 i 4m x 18 gs8662dt19bd-450 sigmaquad-ii+ b4 sram 165-bump bga 450 c 4m x 18 gs8662dt19bd-400 sigmaquad-ii+ b4 sram 165-bump bga 400 c 4m x 18 gs8662dt19bd-350 sigmaquad-ii+ b4 sram 165-bump bga 350 c 4m x 18 gs8662dt19bd-333 sigmaquad-ii+ b4 sram 165-bump bga 333 c 4m x 18 GS8662DT19BD-300 sigmaquad-ii+ b4 sram 165-bump bga 300 c 4m x 18 gs8662dt19bd-450i sigmaquad-ii+ b4 sram 165-bump bga 450 i 4m x 18 gs8662dt19bd-400i sigmaquad-ii+ b4 sram 165-bump bga 400 i 4m x 18 gs8662dt19bd-350i sigmaquad-ii+ b4 sram 165-bump bga 350 i 4m x 18 gs8662dt19bd-333i sigmaquad-ii+ b4 sram 165-bump bga 333 i 4m x 18 GS8662DT19BD-300i sigmaquad-ii+ b4 sram 165-bump bga 300 i 4m x 18 gs8662dt19bgd-450 sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 450 c 4m x 18 gs8662dt19bgd-400 sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 400 c 4m x 18 gs8662dt19bgd-350 sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 350 c 4m x 18 gs8662dt19bgd-333 sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 333 c 4m x 18 gs8662dt19bgd-300 sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 300 c 4m x 18 gs8662dt19bgd-450i sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 450 i 4m x 18 gs8662dt19bgd-400i sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 400 i 4m x 18 gs8662dt19bgd-350i sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 350 i 4m x 18 gs8662dt19bgd-333i sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 333 i 4m x 18 gs8662dt19bgd-300i sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 300 i 2m x 36 gs8662dt37bd-450 sigmaquad-ii+ b4 sram 165-bump bga 450 c 2m x 36 gs8662dt37bd-400 sigmaquad-ii+ b4 sram 165-bump bga 400 c 2m x 36 gs8662dt37ad-350 sigmaquad-ii+ b4 sram 165-bump bga 350 c 2m x 36 gs8662dt37bd-333 sigmaquad-ii+ b4 sram 165-bump bga 333 c ordering information?gsi sigm aquad-ii+ sram (continued) org part number 1 type package speed (mhz) t j 2 notes: 1. for tape and reel add the character ?t? to the end of the part number. example: gs8662dtxxd-300t. 2. c = commercial temperature range. i = industrial temperature range.
gs8662dt07/10/19/37bd-450/400/350/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00b 8/2017 28/28 ? 2011, gsi technology 2m x 36 gs8662dt37bd-300 sigmaquad-ii+ b4 sram 165-bump bga 300 c 2m x 36 gs8662dt37bd-450i sigmaquad-ii+ b4 sram 165-bump bga 450 i 2m x 36 gs8662dt37bd-400i sigmaquad-ii+ b4 sram 165-bump bga 400 i 2m x 36 gs8662dt37bd-350i sigmaquad-ii+ b4 sram 165-bump bga 350 i 2m x 36 gs8662dt37bd-333i sigmaquad-ii+ b4 sram 165-bump bga 333 i 2m x 36 gs8662dt37bd-300i sigmaquad-ii+ b4 sram 165-bump bga 300 i 2m x 36 gs8662dt37bgd-450 sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 450 c 2m x 36 gs8662dt37bgd-400 sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 400 c 2m x 36 gs8662dt37bgd-350 sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 350 c 2m x 36 gs8662dt37bgd-333 sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 333 c 2m x 36 gs8662dt37bgd-300 sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 300 c 2m x 36 gs8662dt37bgd-450i sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 450 i 2m x 36 gs8662dt37bgd-400i sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 400 i 2m x 36 gs8662dt37bgd-350i sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 350 i 2m x 36 gs8662dt37bgd-333i sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 333 i 2m x 36 gs8662dt37bgd-300i sigmaquad-ii+ b4 sram rohs-compliant 165-bump bga 300 i sigmaquad-ii+ sram revision history file name format/content description of changes 8662dt1937b_r1 creation of datasheet (rev1.00a: editorial updates) (rev1.00b: corrected erroneous in formation in input and output leakage characteristics table) ordering information?gsi sigm aquad-ii+ sram (continued) org part number 1 type package speed (mhz) t j 2 notes: 1. for tape and reel add the character ?t? to the end of the part number. example: gs8662dtxxd-300t. 2. c = commercial temperature range. i = industrial temperature range.

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